This invention relates to a semiconductor memory device with high data access speed for preventing selectively data delay in redundancy logic.
In general, dynamic random access memories (DRAMs) which are most widely used among semiconductor memory devices is widely used with the lowest value in the memory portion of the computer main memories and peripheral equipment. In particular, because the semiconductor memory devices are manufactured with microprocessing technique using high integration technology, probability to fail in the main parts of the memory device is high. In general, a technique is used to repair defects with spare elements. The technique is called as redundancy technology and logic embodying the redundancy technology is called as defect repair logic, redundancy logic or spare logic.
The portion of the memory device which is undoubtedly be repaired is a memory cell array. It is because the semiconductor memory chip can not used when any one of memory cells in the memory cell array is defective. The memory device with matrix type includes redundancy logic where spare memory cells are provided in row or in column of the memory cell array and when the defect in any memory cell of memory cell array, the defective memory cell is substituted by the space memory cell. The spare logic is a row redundancy logic and a column redundancy logic.
In general, the memory devices, typical DRAMs, carry out the read and write operation for reading/writing data from/in the memory cell array with commands combined with address. Because the access speed is an essential factor for estimating performance of the memory device, the memory device with high access speed has a superior competitiveness.
However, the redundancy logic circuit has a problem to delay access speed. So as to understand the problem, the operation of typical DRAM will be first described hereinafter.
It uses address multiplexing method that a row address and a column address are provided with time delay in the DRAM. When a row address strobe (RAS) signal is activated, the row address is received and when a column address strobe (CAS) signal is activated, the column address is received so that finally, the selected memory cell is accessed. In DRAM operation, the activation speed of the RAS signal is more important than that of the CAS signal. It is because of DRAMs, synchronous dynamic random access memories (SDRAMs) operates with burst mode that the consecutive CAS activation following one RAS activation so that the data access speed determines the performance of DRAMs.
In particular, SDRAM outputs data in syncronization with clock and generates an external address signal or an internal address signal at a toggle edge of every clock to select a column selection signal. Accordingly, the speed to select the column selection signal determines data access speed with CAS activation.
FIG. 1 shows a block diagram of a DRAM in the prior art. The prior redundancy circuit includes a plurality of address input terminals 10 for receiving an external column address signal Y-add bit by bit; a plurality of address input buffers 20 for converting the external column address signal Y-add through the address input terminals 10 into an internal column address signal bit by bit, each of the address input buffers 20 being corresponding to each of the address input terminals; an address predecoder 30 for predecoding the internal column address signal from the address input buffers 20 to generate global column address signals GAYij; a column redundancy fuse array 40 for receiving the global column address signals GAYij and detecting whether they are redundancy addresses to generate a spare detection signal SD; a redundancy selector 50 for selectively generating a normal column enable signal NCE or a spare column enable signal SCE in accordance with the spare detection signal SD from the column redundancy fuse array 40; an address block repeater for receiving the global column address signals GAYij and the normal column enable signal NCE to generate column address signals BAYij; a column main decoder 70 for receiving the column address signals BAYij from the address block repeater 60 and decoding them to generate column selection signals Yi&lt;n&gt;; and a spare column decoder 80 for receiving the spare column enable signal SCE from the redundancy selector 50 to generate spare column selection signals SYi.
FIG. 2 shows a circuit diagram of the address block repeater in FIG. 1. The address block repeater 60 includes a first delay portion 61 to a fourth delay portion 64 for respectively receiving the predecoded address signals GAY01&lt;0&gt;-GAY01&lt;3&gt; and for delaying them for a selected time which is a desired minimum time for detecting the redundancy; a plurality of a first to a fourth AND logic portions 65-68 for receiving the normal column enable signal NCE and output signals of the delay portions 61-64 to generate column address signals BAY01&lt;0&gt;-BAY&lt;3&gt;.
The delay portions include a plurality of inverters IV1-IV4, IV5-IV8, IV9-IV12 and IV13-IV16 connected in series and the AND logic portions include NAND gate NA1-NA4 and inverter IV17-IV20.
FIG. 3 shows a circuit diagram of the column main decoder in FIG. 1. The column main decoder 70 receives the column address signals BAY&lt;0&gt;-BAY&lt;3&gt; from the address block repeater 60 of FIG. 2 and decodes them to activate any one of the column selection signals Yi&lt;0&gt;-Yi&lt;3&gt;.
FIG. 4 shows a circuit diagram of the column redundancy fuse array in FIG. 1. The column redundancy fuse array includes a PMOS transistor MP1 for precharging the potential of a defect detection node Nd1 with a power voltage Vdd by a precharge signal pcg which is applied to a gate thereof; a plurality of NMOS transistors MN1-MN12 which receive the global column address signals GAY01&lt;0&gt;-GAY45&lt;3&gt; from the address predecoder 30 to drop the potential of the node Nd1 to a ground terminal Vss; a plurality of fuses F1-F12 connected to the defect detection node Nd1 and drains of the NMOS transistors MN1-MN12; a plurality of inverters IV1-IV2 connected to the defect detection node Nd1, for generating the spare detection signal SD.
If the global address signals corresponding to the defect cells are GAY01&lt;0&gt;, GAY23&lt;0&gt; and GAY45&lt;0&gt;, so as to detect the global address signal GAY01&lt;0&gt;, GAY23&lt;0&gt; and GAY45&lt;0&gt;, the fuses F1, F5, F9 connected to the NMOS transistors MN1, MN5 and MN9 where the global address signals are applied to gates become blown by using laser. At this time, if other addresses GAY01&lt;1&gt;-GAY01&lt;3&gt;, GAY23&lt;1&gt;-GAY23&lt;3&gt;, GAY45&lt;1&gt;-GAY45&lt;3&gt; except for the above redundancy address GAY01&lt;0&gt;, GAY23&lt;0&gt; and GAY45&lt;0&gt; are received from the predecoder 30, potential of the defect detection node Nd1 becomes at a ground level Vss by the non-blown fuses F2-F4, F6-F8 and F10-F12 so that it becomes at logic low level. Finally, the column redundancy fuse array 40 generates the spare detection signal SD of logic low level.
On the other hand, if the redundancy addresses GAY01&lt;0&gt;, GAY23&lt;0&gt; or GAY45&lt;0&gt; are received, because the fuses F1, F5, and F9 corresponding to the redundancy address are already blown, the defect detection node Nd1 maintains its initial logic high level. Finally, the redundancy fuse array 40 generates the spare detection signal SD of logic high level.
FIG. 5 shows a circuit diagram of the redundancy selector and the spare column decoder in FIG. 1. The redundancy selector 50 which receives the spare detection signal SD from the column redundancy fuse array 40 to generate the normal column enable signal NCE and a spare column enable signal SCE, includes inverters IV23 and IV25 for inverting the spare detection signals SD(0) and SD(1) and generating output signals NCD(0) and NCD(1), respectively; inverters IV24 and IV26 for inverting the output signals of inverters IV23 and IV25 to generate the spare column enable signals SCE (0) and SCE (1), respectively to the spare column decoder 80; a NAND gate NA5 for carrying out logic NAND of the output signals NCD(0) and NCD(1); an inverter IV27 for inverting an output signal of the NAND gate NA5 to generate the normal column enable signal NCE to the address block repeater 60.
The spare column decoder 80 which receives the spare column enable signals SCE(0) and SCE(1) from the redundancy selector 50 to generate spare column selection signals SY(0) and SY(1), includes NAND gates NA6 and NA7 for receiving output signals SCE(0) and SCE(1) from the redundancy selector 15 as one input signal, respectively and the global column address signal GAY01 predecoded from the predecoder 30 as the other input signal and inverters IV28-IV30 and IV31-IV33 for inverting output signals of NAND gates NA6 and NA7 to generate the spare column selection signals SY(0) and SY(1), respectively.
The redundancy selector 50 controls the address block selection 60 and the spare column decoder 80 in accordance with the spare detection signals SD(0) and SD(1) from the column redundancy fuse array 50.
For example, the normal address signals are received, the redundancy fuse array 40 outputs the output signals SD(0) and SD(1) of logic low level so that the signals SD(0) and SD(1) provided to the redundancy selector 50 are transited into logic low level by the inverters IV23 and IV25. The signals SD(0) and SD(1) of logic low level are transited into the normal column selection signal NCE of logic low level through the NAND gate NA5 and the inverter IV27.
On the other hand, the signals SD(0) and SD(1) of logic low level from the redundancy selector 50 pass the inverters IN23, IV24 and IV25, IV26 without level transition to maintain the logic low level and then provided to the one input signal of the NAND gates NA6 and NA7 of the spare column decoder 80. Accordingly, the output signals of the NAND gates NA6 and NA7 becomes logic high level regardless of the logic level of the global address signal GAY10 predecoded from the predecoder 30 provided as the other input signals of the NAND gates NA6 and NA7 and the redundancy column decoder 80 generates the spare column selection signals SYi(0) and SYi(1) of logic low level through the inverters IV28-IV30 and IV31-IV33.
As above descried, the global column address signals are not directly provided to the column main decoder 70 to degenerate the column selection signal SY(i). They are delayed for the minimum time desired for detecting the repair, that is time delayed through the address block repeater 60. Accordingly, if the redundancy addresses are received, the column main decoder 70 is activated and the spare column decoder 80 is non-activated. On the other hand, if the normal addresses are received, the column main decoder 70 is activated to generate the column selection signal Yi&lt;n&gt;.
As above described, the prior DRAM does not decode the column address signal Yi provided to the main column decoder 70 immediately. Although the normal address is received, the decoding operation is carried out after the desired minimum time, the delay time in the address block repeater 60. Therefore, the high data access speed is decreased.
Besides, in case where the redundancy circuit is provided in row and column of the memory cell array, if all the defects occurred in a chip are repaired by using the row spare redundancy circuit, the other spare column redundancy circuit is not required in the chip any more. Accordingly, unused redundancy circuit makes the data access speed down regardless of redundancy.